Portable computing devices (PCDs) include cellular telephones, portable digital assistants (PDAs), portable game consoles, laptop computers, and other portable electronic devices. PCDs may employ system-on-chip (SOC) architectures which comprise one or more processing cores integrated on the same chip or die. A processing core may have deadlines which, if missed, may cause detectable or visible failures that are not acceptable during operation of the PCD. Such cores are referred to as unacceptable deadline miss (UDM) cores in this disclosure. UDM cores may also be referred to as real time clients/cores (or suitable alternatives known in the art) to convey that deadline misses in real time or during operation of the cores are unacceptable.
In contrast, there may be other cores which may suffer from degradation of performance, but the performance degradation or failures to meet deadlines, for example, may be acceptable. Such cores are referred to as non-UDM cores in this disclosure. Non-UDM cores may also be referred to as non-real time clients/cores or suitable alternatives to convey that deadline misses in real time for the cores are acceptable.
In general, deadlines for a core may be driven by the amount of bandwidth (BW) the core receives from a shared resource such as a memory (e.g., dynamic random access memory (DRAM), internal static random access memory (SRAM) memory (IMEM)), a bus (e.g., peripheral component interconnect express (PCI-e), external transport links), etc., or any shared bandwidth resource. More specifically, the deadlines may be based on the bandwidth made available to the core for a specified period of time. The specified period of time may be relatively small, for example, in the range of 10 to 100 microseconds.
When certain cores do not receive sufficient memory BW over the specified period of time, failures may occur, which may be visible to the user. For example, one of the cores in a PCD may be a display engine which reads data from a memory element (e.g., DRAM) and outputs data to a display panel/device for a user to view. If the display engine is not able to read sufficient data from the DRAM within a fixed period of time, then the display engine may be caused to run out of display data and be forced to display a fixed, solid color (e.g., blue or black) on the display. This is an error condition pertaining to the display engine, and may be referred to in the art as “display underflow,” “display underrun” or “display tearing.” Such display error conditions are considered to be unacceptable, making the display engine a UDM core.
Another example of an unacceptable failure may involve a camera in the PCD. In general, the camera may receive data from a sensor and write that data to the DRAM. However, if the data received by the camera is not written to the DRAM within a fixed period of time, then the camera may become backed up with received data and start losing input data received from the sensor. This is an error condition for the camera and may be referred to as “camera overflow” or “camera image corruption.” The camera error condition can lead to an unacceptable loss of image quality, making the camera a UDM core.
Yet another example of unacceptable failure may relate to a modem core not being able to read/write sufficient data from/to DRAM over a fixed period of time, which can prevent the modem core from completing critical tasks on time. If the critical tasks are not completed within certain deadlines, the modem core's firmware may crash: voice or data calls of a PCD are lost for period of time or an internet connection may appear sluggish (i.e. stuttering during an internet connection). This is an error condition for the modem core which is unacceptable, and so the modem core can also be considered a UDM core.
While the above examples are described as unacceptable deadline misses for particular cores, some cores may be multithreaded processors with two or more parallel processing threads. Multithreaded processors may have additional considerations when it comes to deadline misses. Tasks with unacceptable deadline misses may be run on one or more threads. The threads on which UDM tasks are run may be referred to as UDM threads. Tasks on a UDM thread will lead to unacceptable failure if deadlines are not met. The multithreaded processor may also have one or more non-UDM threads, wherein tasks on non-UDM threads will not lead to unacceptable failures if deadlines are not met.
Managing bandwidths and resources for a multithreaded processor of the PCD which has a mix of UDM and non-UDM threads is challenging. It may be desired to protect UDM threads from being starved of bandwidth/resources by non-UDM threads within the multithreaded processor. Further, a processing system may comprise one or more cores external to the multithreaded processor. Therefore, it may also be desired to protect bandwidth/resources for UDM threads of a multithreaded processor from cores external to the multithreaded processor. Moreover, some processing systems may include more than one multiprocessor, which means that it may also be desired to protect the UDM threads of each multiprocessor from bandwidth/resource degradation.
Accordingly, there is a need in the art for managing bandwidth/resources of a processing system comprising at least one multithreaded processor, wherein the multithreaded processor may comprise at least one UDM thread.